1. Field of the Invention
The present invention relates to level shift circuits for producing an output by changing the voltage amplitude of an input signal. In particular, the invention relates to a level shift circuit suitable for efficiently producing an output signal having a large voltage amplitude from an input signal having a small voltage amplitude.
2. Description of the Related Art
As the electronic devices become increasingly more versatile in terms of the functions they provide, reduction of their power consumption has been an ongoing concern. According to a conventional technology, this need is addressed by causing individual circuits within an electronic device to operate at minimum voltages at which they can operate. As a result, differences have been caused in the signal levels among the individual circuits.
For example, when a digital signal is transmitted from a circuit operating at 2 V to a circuit operating at 5 V, a high-level signal of the circuit operating at 2 V is judged to be a low-level signal by the circuit operating at 5 V. Thus, the signal cannot be transmitted accurately.
In order to overcome this problem, a level shift circuit has been developed, as shown in FIG. 7 and described in Japanese Laid-Open Patent Application No. 11-68534.
In the level shift circuit shown in FIG. 7, a series connection of a PMOS transistor M1 and an NMOS transistor M2 is connected between a high-voltage power supply VH and a ground potential GND. A capacitor C is connected between the gate of the PMOS transistor M1 and the gate of the NMOS transistor M2.
Between the high-voltage power supply VH and the gate of the PMOS transistor M1, there is connected a circuit consisting of a series connection of a diode-connected PMOS transistor M3 and a diode-connected PMOS transistor M4.
A diode D connected between the high-voltage power supply VH and the gate of PMOS transistor M1 is an equivalent diode of the PMOS transistors M3 and M4.
An input terminal IN, to which a low-voltage amplitude signal is inputted, is connected to the gate of the NMOS transistor M2. An output signal of a high voltage amplitude is outputted via an output terminal OUT at the connecting node between the PMOS transistor M1 and the NMOS transistor M2.
FIG. 8 shows a timing chart illustrating an operation of the conventional level shift circuit shown in FIG. 7. The timing chart illustrates the changes in a gate voltage A of the PMOS transistor M1, and a gate voltage B, which is also the input voltage, of the NMOS transistor M2. The timing chart also illustrates the corresponding ON/OFF operations of the PMOS transistor M1 and the NMOS transistor M2.
Vth1 through Vth4 in FIG. 8 indicate the threshold voltages of the MOS transistors M1 through M4, respectively. Vf indicates the forward voltage of the equivalent diode D.
In the following, an operation of the level shift circuit shown in FIG. 7 is described with reference to the timing chart of FIG. 8.
When the input voltage B at the input terminal IN is at a low-level (0V), the NMOS transistor M2 turns off. In this state, the capacitor C is charged by the high-voltage power supply VH via the diode connections of the PMOS transistors M3 and M4. Thus, the gate voltage A of the PMOS transistor M1 becomes “VH−(Vth3+Vth4)”, so that the PMOS transistor M1 turns on.
As the input voltage B increases and exceeds the threshold voltage Vth2 of the NMOS transistor M2, the NMOS transistor M2 turns on. At this time, the gate voltage A of the PMOS transistor M1 is also increased by the effect of the capacitor C with the same slope as the input voltage B, so that the gate voltage A of the PMOS transistor M1 becomes “VH−(Vth3+Vth4)+Vth2”.
Assuming that the PMOS transistors M1, M3, M4, and the NMOS transistor M2 have the same threshold voltages, the gate voltage A of the PMOS transistor M1 becomes “VH−Vth1”, so that the PMOS transistor M1 turns off.
Namely, the PMOS transistor M1 turns off almost simultaneously as the NMOS transistor M2 turns on. Thus, there is hardly any through current due to the PMOS transistor M1 and the NMOS transistor M2.
As the input voltage B further increases, the gate voltage A of the PMOS transistor M1 also increases. However, due to the effect of the equivalent diode D, the voltage is clamped at VH+Vf, so that the charge stored in the capacitor C is discharged to the high-voltage power supply VH. As a result, the voltage across the capacitor C decreases.
As the input voltage B decreases from this state, the gate voltage A of the PMOS transistor M1 also starts decreasing with the same slope.
When the gate voltage A of the PMOS transistor M1 drops to “VH−Vth1”, the PMOS transistor M1 turns on.
However, because the input voltage B at this times is still much higher than the threshold voltage Vth2 of the NMOS transistor M2, the NMOS transistor M2 remains on.
As a result, the PMOS transistor M1 and the NMOS transistor M2 both turn on until the input voltage B further decreases below the threshold voltage Vth2 of the NMOS transistor M2, resulting in a large through current.
While the above discussion is based on the assumption that the MOS transistors M1 through M4 have the same threshold voltages, it is known that the threshold voltage of an actual MOS transistor varies due to manufacturing process variations.
While such a change in threshold voltage occurs in the same direction among transistors of the same conductivity type, the direction of change does not necessarily correspond among transistors of different conductivity types.
Namely, while a group of NMOS transistors or a group of PMOS transistors each may have relatively identical threshold voltages, the threshold voltage may vary between a NMOS transistor and a PMOS transistor. For example, the threshold voltage of the NMOS transistor increases when that of the PMOS transistor decreases, or vice versa.
The following discusses the rise in input voltage B from low-level to high-level in the conventional level shift circuit when the threshold voltage of the NMOS transistor decreases and the threshold voltages of the PMOS transistors increase.
The gate voltage A of the PMOS transistor M1 is VH−(Vth3+Vth4) when the input voltage B is at low-level.
As the input voltage B increases and reaches the threshold voltage Vth2 of the NMOS transistor M2, the gate voltage A of the PMOS transistor M1 is VH−(Vth3+Vth4)+Vth2.
From the aforementioned conditions, Vth1=Vth3=Vth4>Vth2. Thus, the gate voltage A of the PMOS transistor M1 is lower than VH−Vth1. Namely, the PMOS transistor M1 still remains on when the NMOS transistor M2 turns on, so that a large through current flows from the high-voltage power supply VH via the PMOS transistor M1 and the NMOS transistor M2.
Thus, in the conventional level shift circuit, a through current may flow upon inversion of the input voltage B from low-level to high-level due to manufacturing process variations.
The voltage drop across the diode connection of each of the PMOS transistor M3 and the PMOS transistor M4 also varies due to the bias current supplied to these devices. Specifically, the gate voltage A when the PMOS transistor M1 is off varies also depending on the bias current supplied to the PMOS transistor M3 and the PMOS transistor M4. Unless the bias current value is appropriately set, the through current could possibly flow for a longer time.
However, the related art does not discuss the bias current supplied to the PMOS transistor M3 and the PMOS transistor M4.
Thus, there has been the problem that there is the duration of time in which both of the PMOS transistor M1 and the NMOS transistor M2 are on upon inversion of the input voltage B from high-level to low-level, which results in a large through current.